Semiconductor integrated circuit chips are normally designed in view of process variations in forming the circuits. Specifically, process variations are presumed, and semiconductor integrated circuit chips are designed such that they will operate reliably for desired performance within the presumed range of process variation. However, since it is difficult to presume device performance variations, the period of time required to design semiconductor integrated circuit chips is increased, and it is necessary to give timing margins to allow semiconductor integrated circuits to operate in worst-cases, the semiconductor integrated circuit chips thus designed tend to suffer performance reductions.
In view of this process variation in today's technologies, additional design time is likewise required in order to close timing at worst-case conditions, e.g., in the classic four timing corners, on integrated circuit chips. In the classic four timing corners, the four corners are worst-case process and worst-case temperature and voltage; worst-case process and best-case temperature and voltage; best-case process and worst-case temperature and voltage; and best-case process and best-case temperature and voltage. The best-case process with high voltage and low temperature yields fast switching circuits, while worst-case process with low voltage and high temperature yields slow switching circuits. While very few chips are ever produced or operated in these worst-case extremes, designers design for the rare event in which the chips are produced or operated in these extremes. Moreover, because many of the gates formed on the integrated circuit chips are built with larger more powerful FETs to ensure the chips will close timing at worst-case conditions, additional power is required on the chips.
Today, there are several different methods to maintain integrated circuits as operational when process variation causes the chips to be operated out of their specifications, i.e., at worst-case condition. These methods include, but are not limited to, raising the voltage, reducing the frequency, back bias, etc. These methods can be applied for the life of the chip or only after a specified period of time has elapsed.
Other solutions in the marketplace today monitor the chip or areas of the chip performance in order to minimize the chip power. These solutions use performance scan-ring oscillators (PSROs) to monitor performance and to insure the power on the chip stays below a predetermined level. However, as it is the PSRO on the chip being monitored rather than the critical paths themselves, this method results in a very coarse measurement. Further, as other solutions monitor how much margin is in the path for sorting purposes, the path is not continuously monitored.
As a result of the above-noted methods, the chips designed to address production or operation in the worse case extremes needlessly waste power, area and time.